The present invention relates to improved semiconductor integrated circuits, particularly ones containing CMOS logic circuits. More particularly, it relates to technology for effectively suppressing fluctuations and a drop in power-source voltage to achieve a constant power-source voltage and stable high-speed operation over an extended time period.
FIG. 46 schematically illustrates the structure of a conventional semiconductor integrated circuit, in which are shown a plurality of (three in the drawing) semiconductor integrated circuits 1 based on CMOS logic. Each of the semiconductor integrated circuits is composed of a logic input circuit 11, an internal logic circuit 12, and a logic output circuit 13, which are integrally formed on a single semiconductor substrate. External terminals 14 are for achieving external connection. The three semiconductor integrated circuits 1 are mounted on the same printed circuit board 2 and operated with a power-source voltage Vc2l, which is from an external power source 3 and distributed to each of the semiconductor integrated circuits 1 through a common constant-voltage circuit 4 and a power-source line 21.
The constant-voltage circuit 4 is composed of a constant-voltage circuit T41 using a row of diodes and an output MOS transistor T42.
The conventional semiconductor integrated circuit has the following problem.
As shown in FIG. 46, a considerable amount of parasitic resistance Rs and inductance Ls is produced on the power-source line 21 between the constant-voltage circuit 4 and each of the semiconductor integrated circuits 1. Consequently, even though the output voltage Vc2l from the constant-voltage circuit 4 is held constant as shown in FIG. 47, a power-source voltage Vc22 actually supplied to each of the semiconductor integrated circuits 1 may fluctuate due to a voltage drop on the power-source line 21, the superimposition of external noise N, or the like and is not necessarily constant.
As a result, each of the semiconductor integrated circuits 1 becomes susceptible to a misoperation resulting from the fluctuations of the operating power-source voltage Vc22. In particular, a semiconductor integrated circuit using a voltage (e.g., 3 V) lower than a normal voltage value (5 V) has been employed in a contemporary electronic circuit device and associated equipment having a battery as a power source. Since the semiconductor integrated circuit operating at such a low power-source voltage is highly sensitive to fluctuations in power-source voltage, a misoperation is caused by only slight voltage fluctuations resulting from the parasitic resistance Rs or inductance Ls on the power-source line 21.
The power-source voltage may also fluctuate depending on the operation of the internal circuit of the semiconductor integrated circuit 1. Voltage fluctuations may cause RF noise and exert a greater influence on the internal circuit thereof than exerted by a voltage drop, resulting in a misoperation.
Thus, the conventional semiconductor integrated circuit has the problem of high susceptibility to a misoperation resulting from voltage fluctuations on the power-source line, from the superimposed noise, or from the operation of the internal circuit thereof.
To solve the problem, Japanese Laid-Open Patent Publication HEI 6-104720 has proposed a structure having an internal constant-voltage circuit provided therein. However, the structure with the internal constant-voltage circuit increases an area occupied by an LSI and has not given sufficient consideration to the influence of a voltage drop accompanying the provision of the additional constant-voltage circuit.
In general, the semiconductor integrated circuit as shown in FIG. 46 is designed to be operable even when the power-source voltage Vc20 from the external power source 3 fluctuates to some extent. Because allowance has thus been made for the fluctuation of the power-source voltage Vc20, the performance of the semiconductor integrated circuit should be underestimated accordingly. Hence, the semiconductor integrated circuit cannot be designed to deliver performance only under optimum conditions, which presents another problem.
It is therefore an object of the present invention to provide a semiconductor integrated circuit less susceptible to a misoperation resulting from the fluctuation of the voltage on a power-source line or. from the superimposed noise.
To attain the above object, the present invention has adopted the following structures, which will be described briefly:
(1) A constantly operating circuit is provided in the semiconductor integrated circuit to suppress voltage fluctuations.
(2) Voltages from two power sources are supplied to the internal circuit of the semiconductor integrated circuit to suppress a voltage drop.
(3) A capacitor element and a power-source monitor line are provided for the internal circuit of the semiconductor integrated circuit so that charges are supplied from the capacitor element to the internal circuit when the power-source monitor line detects a voltage drop in the internal circuit, thereby suppressing a voltage drop.
(4) A redundant power-source line is provided in mask design for the semiconductor integrated circuit to suppress a voltage drop.
Specifically, a semiconductor integrated circuit according to the present invention comprises: a power-source line and a ground line; a logic circuit portion composing a logic circuit and connected to the power-source line and ground line; and a constant-voltage auxiliary circuit connected, in parallel with the logic circuit portion, to the power-source line and ground line, the constant-voltage auxiliary circuit consuming power by causing a current to flow from the power-source line to the ground line in a stable state in which an output value from the logic circuit portion does not vary and halting the power consumption when the output value from the logic circuit portion varies.
Alternatively, the semiconductor integrated circuit according to the present invention comprises: a plurality of logic circuits; a first power-source line connected to each of the logic circuits and carrying a specified power-source voltage; a second power-source line different from the first power-source line; and a voltage supplying circuit connected to the first and second power-source lines, the voltage supplying circuit detecting a variation in any of voltages supplied from the first power-source line to the logic circuits from the value of the specified power-source voltage to another value and supplying, upon detection, a voltage from the second power-source line to the first power-source line.
Alternatively, the semiconductor integrated circuit according to the present invention comprises: an internal semiconductor circuit; a power source connected to the internal semiconductor circuit; a first power-source monitor line for monitoring a level of a power-source voltage supplied from the power source to the internal semiconductor circuit; a second power-source monitor line for monitoring a level of the power-source voltage inside the internal semiconductor circuit when the internal semiconductor circuit is in operation; and a level-fluctuation compensator connected to the first and second power-source monitor lines, the level-fluctuation compensator detecting fluctuations in the level of the. internal power-source voltage when the internal semiconductor circuit is in operation and adjusting, upon detection of fluctuations in the level of the operating voltage, the power-source voltage inside the internal semiconductor circuit to be equal in level to the power-source voltage from the power source.
An automatic layout method for a plurality of semiconductor macro cells according to the present invention involves the use of a computer and comprises a clustering step of placing the plurality of macro cells comprising: a high-power-cell retrieving step of retrieving, from the plurality of macro cells, ones each consuming high power; and a pairing step of adding a charge-accumulating cell to each of the high-power-consumption macro cells retrieved in the retrieving step to pair each of the high-power-consumption macro cells with one charge-accumulating cell.
Alternatively, the automatic layout method for a plurality of semiconductor macro cells according to the present invention involves the use of a computer and comprises a macro-cell placing step of placing the plurality of macro cells comprising: a high-power-cell retrieving step of retrieving, from the plurality of macro cells, ones each consuming high power; and a placement step of placing the plurality of high-power-consumption macro cells retrieved in the high-power-cell retrieving step such that a maximum allowable spacing is provided between the individual high-power-consumption macro cells.
Alternatively, the automatic layout method for a plurality of semiconductor macro cells according to the present invention involves the use of a computer and comprises a macro-cell placing step of placing the plurality of macro cells comprising: a high-power-cell retrieving step of retrieving, from the plurality of macro cells, ones each consuming high power; a position specifying step of specifying a position at which a basic power-source line is to be placed; a placement step of placing each of the plurality of high-power-consumption macro cells retrieved in the high-power-cell retrieving step at a reduced distance from the basic power-source line the position of which has been specified in the position specifying step.
Alternatively, the automatic layout method for a plurality of semiconductor macro cells according to the present invention involves the use of a computer and comprises a macro-cell placing step of placing the plurality of macro cells comprising: a high-power-cell retrieving step of retrieving, from the plurality of macro cells, ones each consuming high power; a position specifying step of specifying a position at which a basic power-source line is to be placed; a power-source-terminal-point retrieving step of retrieving a point of a power-source terminal of each of the high-power-consumption macro cells; a connecting-point retrieving step of retrieving such a connecting point on the basic power-source line as to minimize a distance between the point of the power-source terminal of the high-power-consumption macro cell and the basic power-source line; and a power-source-auxiliary-line routing step of wiring the point of the power-source terminal of the high-power-consumption macro cell to the connecting point on the basic power-source line with a power-source auxiliary line.
Alternatively, the automatic layout method for a plurality of semiconductor macro cells according to the present invention involves the use of a computer and comprises a macro-cell placing step of placing the plurality of macro cells comprising: a high-power-cell retrieving step of retrieving, from the plurality of macro cells, ones each consuming high power; and a power-source-auxiliary-line routing step of wiring an in-cell power-source line supplying power to any of the high-power-consumption macro cells retrieved in the high-power-cell retrieving step and another in-cell power-source line not supplying power to the high-power-consumption macro cells with a power-source auxiliary line.
A mask processing method for a semiconductor macro cell according to the present invention comprises a mask processing step for the semiconductor macro cell using a computer comprising: a power-source-line-configuration retrieving step of retrieving a power-source-line configuration from an entire region occupied by the cell; an inverted-geometry generating step of generating an inverted geometry corresponding to the entire region occupied by the cell except for power-source lines and wiring in a wiring layer containing the power-source lines; a dividing step of dividing the generated inverted geometry into a plurality of geometries; a mask operation step of adding the post-division inverted geometries to the retrieved power-source-line configuration; and a power-source-line reducing step of reducing the power-source-line configuration including the additional post-division inverted geometries by the magnitude of a specified minimum wire spacing.
A semiconductor macro cell according to the present invention comprises a wiring layer containing power-source lines, wherein the power-source lines and wiring other than the power-source lines are disposed in the. wiring layer, the power-source lines being placed over an entire region at a distance equivalent to a specified minimum wire spacing from the wiring.
Thus, according to the present invention, the constant-voltage auxiliary circuit consumes power when the output from the logic circuit portion is stable, i.e., when the power-source voltage is stable, so that the power-source voltage is held constant at a given value. On the other hand, the constant-voltage auxiliary circuit halts power consumption when the output from the logic circuit portion is inverted, i.e., when the logic circuit power consumes power to cause the fluctuation of the power-source voltage, so that the power-source voltage is also held constant at the given value.
When a voltage is supplied from the first power-source line to the internal logic circuit of the semiconductor integrated circuit and the internal logic circuit operates to consume power and cause voltage fluctuations, the voltage supplying circuit operates to cause the second power-source line to supply power to the first power-source line, so that voltage fluctuations are effectively suppressed.
Moreover, when the internal power-source voltage is lowered in level or the ground voltage is increased in level during the operation of the internal semiconductor circuit, the level-fluctuation compensator operates to cause the charge accumulator to supply charges to the internal semiconductor circuit or the charge releaser to extract charges from the internal semiconductor circuit, so that fluctuations in voltage level in the internal semiconductor circuit is suppressed.
Furthermore, since the present invention has added the respective charge-accumulating cells to the plurality of macro cells each consuming high power, placed each of the high-power-consumption macro cells in the vicinity of the basic power-source line, connected the high-power-consumption macro cell to the basic power-source line with the auxiliary power-source line, or connected the power-source line of a macro cell consuming only a small amount of power to the high-power-consumption macro cell with the auxiliary power-source line in mask design of the semiconductor integrated circuit, a drop in voltage supplied to the high-power-consumption macro cell can be minimized.
Additionally, since the semiconductor macro cell according to the present invention has a power-source line having a maximum allowable thickness, the power-source line itself functions as a capacitor to stabilize a power supply to the semiconductor macro cell.